Implementation of cryptographic algorithms for the RISC-V instruction set architecture in two cases

This new technical paper titled “Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms” was published by researchers at Intel, North Arizona University, and Google, with partial funding from the US Air Force Research Laboratory.

“The ever-increasing need to secure computer systems using cryptographic algorithms is driving interest in the effective implementation of common algorithms. Although algorithms can be implemented in software using basic instruction sets, there is considerable potential to reduce memory cost and improve speed using specialized instructions and associated hardware. . However, there is a need to assess the benefits and costs of software implementations and new instructions that implement key cryptographic algorithms in fewer cycles. The main objective of this article is to improve understanding of the performance and implementation cost of cryptographic algorithms for the RISC-V Instruction Set Architecture (ISA) in two cases: software implementations of algorithms using the rv32i instruction set and using supported cryptographic instructions. by dedicated hardware in additional functional units. In both cases, we describe a RISC-V processor with cryptographic hardware extensions and hand-optimized RISC-V assembly language implementations of eleven cryptographic algorithms. Compared to implementations with only the rv32i instruction set, implementations with the crypto set extension provide 1.5× to 8.6× faster and 1.2× to 5.8× execution speed less program memory for five of the eleven algorithms. Based on our performance analyses, a new instruction is proposed to increase the efficiency of the algorithm implementation.

Find it spec sheet here. Published in August 2022.

Nişanci, G.; Flikkema, PG; Yalçın, T. Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms. Cryptography 2022, 6, 41.

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